1. Field of the Invention
This invention relates to a sense amplifier, and more particularly to a sense amplifier which is used in a semiconductor memory device and has a function of amplifying a signal flowing in a bit line and transmitting the amplified signal to a data line.
2. Description of the Related Art
At present, in a typical dynamic semiconductor memory device, paired bit lines are connected to a memory cell and a potential difference between the paired bit lines is amplified by a sense amplifier so as to amplify a signal flowing in the bit line.
The sense amplifier includes a sense circuit for sensing and amplifying a potential difference between the paired bit lines. As the sense amplifier, a sense amplifier having two transistors cross-coupled between the paired bit lines is generally used.
Further, bit line pairs of a number corresponding to a preset number of columns are provided. When data is read out from a memory cell or data is written into a memory cell, a desired bit line pair is selected from a plurality of bit line pairs by a column selection signal output from a column decoder. A column gate is provided between the bit line pair and the data line pair to electrically connect or disconnect the bit line pair to or from the data line pair according to the column selection signal.
FIG. 1 is a general circuit diagram of this type of circuit. In FIG. 1, one column (one bit line pair) is shown.
As shown in FIG. 1, a bit line BL and an inverted bit line BBL (in this specification, the head symbol "B" indicates an inverted signal) which makes a pair with the bit line BL are provided to make a bit line pair in a semiconductor memory device.
A sense amplifier circuit 4 is connected between the paired bit lines BL and BBL and is constructed by N-channel MOSFETs (which are hereinafter referred to as NMOSs) Q1 and Q2 and P-channel MOSFETs (which are hereinafter referred to as PMOSs) Q5 and Q6.
The source of the NMOS Q1 is connected to an inverted sense signal line BSAN, the drain thereof is connected to the bit line BL, and the gate thereof is connected to the inverted bit line BBL. The source of the NMOS Q2 is connected to the inverted sense signal line BSAN, the drain thereof is connected to the inverted bit line BBL, and the gate thereof is connected to the bit line BL. The source of the PMOS Q5 is connected to a sense signal line SAN, the drain thereof is connected to the bit line BL, and the gate thereof is connected to the inverted bit line BBL. The source of the PMOS Q6 is connected to the sense signal line BSAN, the drain thereof is connected to the inverted bit line BBL, and the gate thereof is connected to the bit line BL.
Further, a column gate 5 is connected between paired data lines DQ, BDQ on one hand and connection nodes between the sense circuit and the paired bit lines BL, BBL on the other. The column gate 5 includes NMOSs Q3 and Q4.
The source of the NMOS Q3 is connected to the bit line BL, the drain thereof is connected to the data line DQ, and the gate thereof is connected to a column selection signal line CSL. The source of the NMOS Q4 is connected to the inverted bit line BBL, the drain thereof is connected to the inverted data line BDQ, and the gate thereof is connected to the column selection signal line CSL.
As described above, in the general circuit, four NMOSs and two PMOSs are used for one column. In order to form the transistors in the semiconductor substrate, it is necessary to form a region for isolating the transistors from one another, that is, an element isolation region such as a field oxide film so as to provide an element region on the semiconductor substrate. Since the sense amplifier has six elements, six element regions are basically required.
Particularly, when attention is given only to the NMOS circuit portion, four element regions must be provided.
However, in the above sense amplifier, particularly in the NMOS circuit portion, four element regions must be provided, and therefore, there occurs a problem that an area occupied by the element isolation region on the substrate is increased. This makes it difficult to reduce the size of the chip.